Programme > Invited Talks

Three decades of arc-free reproducible CDM-like ESD testing from VF-TLP to CC-TLP

Horst Gieser, Heinrich Wolf, Johannes Weber and Ellen Jirutkova, Fraunhofer EMFT, Germany

Charged Device Model CDM represents today’s reality of electrostatic risk during highly automated assembly, test and  heterointegration of microelectronic circuits. There was no doubt about the failure signatures mainly in gate oxides behind the protection, between supply nets or in charge pumps and the need to test for their robustness. About 30 years ago the discussion started how discharge events with ps-risetimes and sub-nanosecond duration can be generated and captured with high fidelity and reproducibility and standards were developed at ESD Association and JEDEC. Nevertheless reproducibility between test systems even at the same test site and even repeatability within a single system became a resource consuming nightmare. Reason were the constructions of the test systems, the inadequate metrology for true-ps-transients and last but not least the variability of the switching spark of the air discharge.  Therefore, a European team has developed the first arc free method with only a single pin in the discharge path - the Capacitively Coupled Transmission Line Pulsing cc-TLP. A remotely generated ps-rise time impulse is injected via a single short contact needle into the capacitance of an IC in a package, on a wafer or even as a bare die. Few mm-short means low-inductive. The contact geometry reaches from tin ball size down to some 10 µm pad sizes with an option for less. The repeatability is improved from more than 20 % of air-CDM to less than 3 % even for very low stress voltages of less than 10 V that become critical for single-digit nm technologies and heterointergation of chiplets into multichip modules. Finally in 2022, after many publication of correlation data and test setups in use at major stake holders the cc-TLP method has made it into a standard document of the ESD Association. The talk gives an overview over a long lasting journey which certainly has not reached its final destination.

New reliability challenges for 3D integration stacking using hybrid bonding

Sandrine Lhostis, STMicroelectronics, France

Improving efficiency and performance is the main driver for microelectronic applications. The new trend named beyond Moore’s law refers to the emergence of new architectures, processes, devices and materials. 3D stacking is definitely an enabler for new architectures and packaging. During the last ten years, many demonstrations were done showing that stacking dies of different technologies enable new functionalities for optical sensor, memories and CPU devices. Increasing the interconnect number by reducing the inter- connection pitch between top and bottom tiers is key to get faster devices. Hybrid bonding, based on oxide- to-oxide and metal-to-metal direct bonding between the reported tiers, is a path for one of the most scalable integrations. We are interested here in the robustness of the hybrid bonding level when decreasing the inter- connection pitch below submicrometric dimensions. The different features for reliability requirements are reviewed and discussed towards standard Back-End-Of-Line interconnects robustness.
Many integration flows have been developed for hybrid bonding stacking. The most critical integration scheme in terms of potential metal diffusion is based on a hybrid bonding interface made of silicon oxide and copper. We have developed a specific integration that is immune to copper diffusion into the faced oxide. This interface stability is assessed towards potential atomic and ionic diffusion. The integrity of the hybrid bonding interface towards Cu diffusion is confirmed by dedicated Time Dependent Dielectric Breakdown studies through a novel test method. A different dependence between time-to-failure and electrical field is observed for the Cu/SiO2 hybrid bonding configuration than for standard BEOL interconnects. Another potential concern for a device is the repetitive thermomechanical stresses that could lead to interface delam- ination in the case of hybrid bonding integration. With pitch reduction, higher stress is expected at the bond- ing level due to the reduced spacing between the pads. This point is assessed by Thermal Cycling tests for pitch reduction. Stress induced Voiding (SiV) may also be a concern. This failure mechanism is driven by the grain microstructure. In our developed integration, reducing the bonding pad size leads to the modifi- cation of the copper microstructure from polycrystalline to one-grain-dominant feature. However, no modification of the robustness to SiV is identified even for bonding pad width reduced to 300nm. Relia- bility under electron flow and thermal stress is performed through electromigration tests. Previous studies on large interconnect pitch have shown that the hybrid bonding level behaves as a standard BEOL level with failure occurring in the feeding lines. With sub-micron pad width reduction, a modification in the failure mechanism is identified. The extracted lifetime is still in line with the specifications.
In-depth studies on the Cu/SiO2 hybrid bonding level indicate that this specific integration is robust to stand- ard failure mechanisms for wafer -to-wafer interconnect pitch down to 710nm and pad width of 300 nm.

Sandrine Lhostis has more than 20 years’ experience in the field of advanced R&D process developments for semi-conductor industry. She received a phD degree in Science and Materials Engineering in 2004 and owns an engineering degree in Materials Science from ECPM (European school for Chemistry, Materials and Polymers). She is member of Technical Staff at STMicroelectronics since 2016. She is now part of the Advanced R&D team of the Technology for Optical Sensors department at STMicroelectronics. Her technical background is the development of disruptive materials for microelectronics application, from high-k materials 20 years ago, then Phase Change Memory materials and lastly Quantum Films materials, combined with the development of advanced process integration solutions. Through several collaborative projects, she is working for more than 10 years on 3D integration solutions and has developed a strong expertise in 3D stacking using hybrid bonding. She currently leads developments on the reliability of the hybrid bonding level for the future generation of devices.

DC and RF Reliability, Failure Mechanisms and Predictive Life Models for 5G/mmW capable GaN HEMT Process

Satyaki Ganguly, Wolfspeed Inc, USA

Wolfspeed has demonstrated reliable, high power, high efficiency, high gain and high frequency RF-GaN on SiC discrete and MMIC devices for both general purpose (military, aerospace, civil, industrial, and scientific) and wireless applications up through 30 GHz (Ka band). In this presentation, Wolfspeed’s various GaN process technology nodes, key device features, various failure modes/mechanisms relevant for GaN devices and overcoming challenges stemming from such failure modes under both DC and RF operation will be discussed in detail. Moreover, the comprehensive DC (both on and off state) and RF reliability assessment, technology qualification and device lifetime modeling (under both DC and RF) will be presented here for Wolfspeed’s Ka band capable 28 V rated 150-nm gate length process technology (G28V5). Last but not the least, reliability without hermeticity (RWoH) which is a germane topic for certain applications including 5G, will be discussed in the light of latest advancement of Wolfspeed’s 5G capable devices.

Dr. Satyaki Ganguly is a Senior Reliability Manager at Wolfspeed, Inc, working with various technologies and material systems including GaN-on-SiC HEMT discrete and MMICs for RF and microwave applications, SiC Schottky power diodes, SiC power MOSFETs and modules. Apart from SiC and GaN, he has expertise in highly integrated silicon CMOS technology through his previous tenure at Intel in production technology development group at Portland, Oregon. Dr. Ganguly holds multiple patents, has co-authored multiple book chapters, many conference and journal papers and serves as a lead and member in many JEDEC (JC14, JC70) and Conference (IEEE IRPS, ROCS etc) technical program committees. Dr. Ganguly earned his Ph.D. in electrical engineering from the University of Notre Dame, Indiana under the supervision of Dr. Debdeep Jena. His graduate research includes design, epitaxy, characterization, fabrication, measurement and simulation of novel III-nitride HEMT devices.

An overview of numerical modeling techniques and case studies for thermal management in power electronics

Nicola Delmonte, University of Parma, Italy

Electronics cooling, although subject of study since the first semiconductor devices dawn, is still of great interest today, especially for the miniaturization of components and power modules. The increasing power density and the required high reliability are the reason to seek new solutions with new tools. They are important because thermal management is a key point of power converters determining heat flow and temperature cycling which can affect performances.
Thus, an overview of cooling techniques for power electronics and tools to simulate heat spreading will be shown together with some study cases.
The aim is to show how coupled multiphysics models can be used for cooling system design or reliability-oriented studies.

Recent progress in vertical GaN power devices on foreign substrates and its implications for their reliability

Max Reimer, Robert Bosch GmbH, Germany

The industrialization of vertical GaN technology is an appealing goal, aiming to overcome the limitations posed by expensive and small-diameter native GaN wafers. To achieve this, the fabrication of vertical GaN power transistors on foreign substrates is exploited. By utilizing hetero epitaxial growth of GaN on e.g. silicon or sapphire, the high production costs and limited availability of native GaN wafers can be circumvented. However, this approach involves a challenging process where the substrate and epitaxial buffer layers beneath the active area must be removed to enable vertical current flow, leading to the creation of thin membrane transistors. Such a vertical membrane transistor architecture with hetero epitaxial GaN (thus strained and more defective) is not only new from a fabrication point of view but also raises questions concerning the reliability of the devices. The ongoing efforts in this domain are part of the EU-funded YESvGaN project. Important milestones which will be discussed are for example the demonstration of avalanche capability of GaN-on-sapphire epitaxial layers, processing of fully vertical diodes on full wafers and initial steps towards the assembly of these thin dies.
The developments made through this project hold significant potential for advancing vertical GaN technology. Successful implementation can pave the way for scalable, cost-effective, and reliable production methods, driving the widespread application of vertical GaN power transistors in various industries.